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BSI BS IEC 62530:2021

SystemVerilog. Unified Hardware Design, Specification, and Verification Language
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BSI BS IEC 62530:2021

SystemVerilog. Unified Hardware Design, Specification, and Verification Language

PUBLISH DATE 2021
PAGES 1320
BSI BS IEC 62530:2021

This standard provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.

SDO BSI: British Standards Institution
Document Number IEC 62530
Publication Date Aug. 19, 2021
Language en - English
Page Count 1320
Revision Level
Supercedes
Committee EPL/501
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