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BSI BS IEC 62880-1:2017

Semiconductor devices. Stress migration test standard -- Copper stress migration test standard
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BSI BS IEC 62880-1:2017

Semiconductor devices. Stress migration test standard -- Copper stress migration test standard

PUBLISH DATE 2020
PAGES 28
BSI BS IEC 62880-1:2017

This part of IEC 62880 describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method can be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time.

Dual damascene Cu metallization systems usually have liners, such as tantalum (Ta) or tantalum nitride (TaN) on the bottom and sides of trenches etched into dielectric layers. Hence, for structures in which a single via contacts a wide line below it, a void under the via can cause an open circuit at almost the same time as any percentage resistance shift that would satisfy a failure criterion.

SDO BSI: British Standards Institution
Document Number IEC 62880-1
Publication Date July 21, 2020
Language en - English
Page Count
Revision Level
Supercedes
Committee EPL/47
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