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IEC 60191-6 Ed. 3.0 b:2009

Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
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IEC 60191-6 Ed. 3.0 b:2009

Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

PUBLISH DATE 2009
PAGES 80
IEC 60191-6 Ed. 3.0 b:2009

Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

IEC 60191-6:2009 gives general rules for the preparation of outline drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3.

It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits classified as form E in Clause 3 of IEC 60191-4.

This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004, and constitutes a technical revision.

This edition includes the following significant changes with respect to the previous edition:

  • a) Scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8;
  • b) Editorial modifications on several pages; and
  • c) Technical revision to ball grid array package (BGA), especially its geometrical drawing format. (Two types of BGA would unify as one type as a result of revising drawing format.)
SDO IEC: International Electrotechnical Commission
Document Number IEC 60191
Publication Date Nov. 1, 2009
Language b - English & French
Page Count
Revision Level 3.0
Supercedes
Committee 47D
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