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IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
Revision Standard - Inactive-Withdrawn.
This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic.
A standard syntax and semantics for VHDL register-transfer level synthesis is defined.
The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.
The standard describes a standard syntax and semantics for VHDL RTL synthesis.
It defines the subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain.
The intent of this revision is to include a maximum subset of VHDL that can be used to describe synthesizable RTL logic.
This includes considering:
The purpose of the standard is to define a syntax and semantics that can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools use the IEEE 1076 standard.
The original standard defined a syntax and semantics that was common amongst all synthesis tools at the time that it was created.
The new standard expands the original purpose by including a maximal subset of VHDL that can be synthesized.
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