Logo
Login Sign Up
Current Revision

IEEE 1285-2005

IEEE Standard for Scalable Storage Interface
Best Price Guarantee
Instant

$119.00


Sub Total (1 Item(s))

$ 0.00

Estimated Shipping

$ 0.00

Total (Pre-Tax)

$ 0.00


View in Library
or
Institute of Electrical and Electronics Engineers Logo

IEEE 1285-2005

IEEE Standard for Scalable Storage Interface

PUBLISH DATE 2010
PAGES 140
IEEE 1285-2005

New IEEE Standard - Inactive-Reserved.

This document specifies a scalable interface between mass-storage devices and controlling hardware/software.

The interface has been optimized for low-latency interconnects, assuming that the processor/controller and the storage device can often be co-located on the same printed-circuit board.

The interface can also be used with longer-distance bus-like interconnects, including (but not limited to):

  • IEEE Std 1394-1995 Serial Bus
  • IEEE Std 1596-1992 Scalable Coherent Interface

This standard defines a scalable interface for use with memory-mapped storage units and other devices.

The term "storage unit" can encompass rotating, non-rotating, volatile, and non-volatile storage.

Issues of concurrency, latency, bandwidth, extensibility, and negotiation will be addressed.

The interface is intended for use with either a single storage unit or with many coordinated storage units.

This standard provides an ***efficient physical-layer independent interface architecture*** for storage units that attach directly to memory access buses.

In this interface model, storage units have an attachment to main memory, rather than an attachment to an I/O channel.

This simplifies the storage unit design and supports scheduling of data transfers spanning large numbers of units.

SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 1285
Publication Date Dec. 8, 2010
Language en - English
Page Count 136
Revision Level
Supercedes
Committee Microprocessor Standards Committee
Loading...

Failed to load document history.

Publish Date Document Id Type View