Current Revision

IEEE 1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

$307.00

Sub Total (1 Item(s))

$ 0.00

Estimated Shipping

$ 0.00

Total (Pre-Tax)

$ 0.00

I have read and agree to the Terms & Conditions

IEEE 1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

PUBLISH DATE 2020

PAGES 458

IEEE 1800.2-2020

Document Information

Revision Standard - Active. The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)

This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800(TM).

Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.


SDO	IEEE: Institute of Electrical and Electronics Engineers
Document Number	1800.2
Publication Date	Sept. 14, 2020
Language	en - English
Page Count	26
Revision Level
Supercedes
Committee	Design Automation

Publish Date	Document Id	Type	View
Sept. 14, 2020	1800.2-2020	Revision
May 26, 2017	1800.2-2017	Revision

SDO	Document	Title
IEEE	IEEE 1076/INT	IEEE Standards Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
IEEE	IEEE 1666	IEEE Standard for Standard SystemC® Language Reference Manual
IEEE	IEEE/IEC 62530-2	IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual
IEEE	IEEE 1666.1	IEEE Standard for Standard SystemC(R) Analog/Mixed-Signal Extensions Language Reference Manual
IEEE	IEEE 1076	IEEE Standard for VHDL Language Reference Manual
IEC	IEC 62530-2	SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
BSI	BSI BS IEC 62530-2	SystemVerilog -- Universal Verification Methodology Language Reference Manual
IEEE	IEEE 1450.2	IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for DC Level Specification
IEEE	IEEE 1450.3	IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std. 1450-1999) for Tester Target Specification
IEEE	IEEE 1647	IEEE Standard for the Functional Verification Language e
IEEE	IEEE 310	IEEE Standard for Reference-Standard Electrical Resistors
ASHRAE	ASHRAE Standard 55 User's Manual	ASHRAE Standard 55 User's Manual
ASHRAE	ASHRAE Standard 90.1 User's Manual	ASHRAE Standard 90.1 User's Manual
BSI	BSI BS IEC 61691-8	Behavioural languages -- Standard SystemC Analog/Mixed-Signal Extensions Language Reference Manual
IEEE	IEEE 1450.1	IEEE Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments
IEC	IEC 61691-8	Behavioural languages - Part 8: Standard SystemC Analog/Mixed-Signal Extensions Language Reference Manual
IEEE	IEEE 1802.3	IEEE Conformance Test Methodology for IEEE Standards for Local and Metropolitan Area Networks - Specific Requirements - Part 3: Carrier Sense Multiple Access With Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications
IEEE	IEEE 1505.3	IEEE Standard for the Universal Test Interface Framework and Pin Configuration for Portable/Benchtop Test Requirements Utilizing IEEE 1505(TM) Receiver Fixture Interface Standard
IEEE	IEEE/IEC 61691-1-1	IEC/IEEE International Standard - Behavioural languages - Part 1-1: VHDL Language Reference Manual
IEEE	IEEE 823	IEEE Standard Methodologies for Specifying Voicegrade Channel Transmission Parameters and Evaluating Connection Transmission Performance for Speech Telephony
IEEE	IEEE 200	IEEE Standard Reference Designations for Electrical and Electronics Parts and Equipments
IEEE	IEEE 1175	IEEE Standard Reference Model for Computing System Tool Interconnections
IEEE	IEEE 1450.6	IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data-Core Test Language (CTL)
IEEE	IEEE 1823	IEEE Standard for Universal Power Adapter for Mobile Devices
IEEE	IEEE 1483	IEEE Standard for Verification of Vital Functions in Processor-Based Systems Used in Rail Transit Control

IEEE 1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

IEEE 1800.2-2020

Document Information

Terms of Service

Conditions of Use

Privacy Policy

Copyright

Communications

Privacy Policy

Cookie Notice