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Information technology - RapidIO(TM) interconnect specification
The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard.
The architecture is targeted toward networking, telecom, and high performance embedded applications.
It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels.
It provides a rich variety of features including:
as well as providing globally shared memory, message passing, and software managed programming models.
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