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IEC 62878-2-5 Ed. 1.0 b:2019

Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate
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IEC 62878-2-5 Ed. 1.0 b:2019

Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate

PUBLISH DATE 2026
IEC 62878-2-5 Ed. 1.0 b:2019
Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate
IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers.
IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.
SDO IEC: International Electrotechnical Commission
Document Number IEC 62878
Publication Date April 1, 2026
Language b - English & French
Page Count
Revision Level 1.0
Supercedes
Committee 91
Publish Date Document Id Type View
April 1, 2026 IEC 62878-2-5 Ed. 1.0 en:2019 Revision
Sept. 1, 2019 Revision
April 1, 2026 IEC 62878-2-5 Ed. 1.0 b:2019 Revision
June 5, 2024 Revision